library verilog;
use verilog.vl_types.all;
entity EPLLB is
    generic(
        FIN             : string  := "100.0";
        CLKI_DIV        : string  := "1";
        CLKOP_DIV       : string  := "8";
        CLKFB_DIV       : string  := "1";
        FDEL            : string  := "0";
        WAKE_ON_LOCK    : string  := "OFF";
        LOCK_CYC        : integer := 2;
        FB_MODE         : string  := "CLOCKTREE"
    );
    port(
        CLKI            : in     vl_logic;
        RST             : in     vl_logic;
        CLKFB           : in     vl_logic;
        CLKOP           : out    vl_logic;
        LOCK            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of FIN : constant is 1;
    attribute mti_svvh_generic_type of CLKI_DIV : constant is 1;
    attribute mti_svvh_generic_type of CLKOP_DIV : constant is 1;
    attribute mti_svvh_generic_type of CLKFB_DIV : constant is 1;
    attribute mti_svvh_generic_type of FDEL : constant is 1;
    attribute mti_svvh_generic_type of WAKE_ON_LOCK : constant is 1;
    attribute mti_svvh_generic_type of LOCK_CYC : constant is 1;
    attribute mti_svvh_generic_type of FB_MODE : constant is 1;
end EPLLB;
